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更新时间:2019-11-14 19:11:35

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Verilog Automatic

by Tian-Changsong ST2/ST3 Trending

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

Details

  • 2013.08.06.08.11.47
  • github.​com
  • github.​com
  • 6 years ago
  • 17 minutes ago
  • 7 years ago

Installs

  • Total 13K
  • Win 9K
  • OS X 2K
  • Linux 2K
Nov 14 Nov 13 Nov 12 Nov 11 Nov 10 Nov 9 Nov 8 Nov 7 Nov 6 Nov 5 Nov 4 Nov 3 Nov 2 Nov 1 Oct 31 Oct 30 Oct 29 Oct 28 Oct 27 Oct 26 Oct 25 Oct 24 Oct 23 Oct 22 Oct 21 Oct 20 Oct 19 Oct 18 Oct 17 Oct 16 Oct 15 Oct 14 Oct 13 Oct 12 Oct 11 Oct 10 Oct 9 Oct 8 Oct 7 Oct 6 Oct 5 Oct 4 Oct 3 Oct 2 Oct 1 Sep 30
Windows 4 11 18 13 0 5 11 12 7 9 12 7 8 11 10 9 8 6 4 8 6 8 3 14 8 10 5 6 5 6 5 4 1 9 9 9 12 8 5 1 7 7 8 6 5 2
OS X 1 2 3 2 2 2 2 3 1 1 1 1 1 2 3 0 0 1 1 0 0 2 0 0 1 3 2 0 3 0 0 1 0 0 2 1 2 1 0 1 0 0 0 0 0 1
Linux 2 2 4 3 1 2 5 1 1 3 0 1 0 3 2 2 2 3 1 0 1 0 1 3 1 0 1 3 2 4 3 2 1 3 2 0 1 2 6 2 0 2 1 2 1 2

Readme

Source
raw.​githubusercontent.​com

Verilog Automatic

This plugin can automatically add ports to the current editing file, generate module instances (need ctags),add instance connections ,add file header for verilog code. Both verilog-1995 and verilog-2001 style are supported. I borrowed the idea from automatic.vim which is a similar plugin for VIM, I just rewrote one for sublime text2&3.

Features


  • AutoPort
  • AutoInst
  • AutoDef
  • AddFileHeader

Description

AutoPort:(shift+f6)


Automatically add ports to the current editing file after the “/autoport/” mark.

  • NOTE: NOT SUPPORTED STYLE:

    input clk,output single_out,   //multiple input/output/inout keywords in the same line
    input clk,rst,
    chip_en;    //multiple signals separated by comma written in different lines
    
  • NOTE: Do not use this function when there are multiple modules in the same file.

Example:

Before

(verilog-1995 style):

module test(/*autoport*/);
    input [1:0]a;
    input b;
    output [2:0]c,d;
    inout e;

(verilog-2001 style):

module test(/*autoport*/);
    input wire[1:0]a;
    input wire b;
    output reg [2:0]c,d;
    inout wire e;

After:

module test(/*autoport*/
//inout
            e,
//output
            c,
            d,
//input
            a,
            b);

AutoInst:(shift+f7)


Automatically generate module instances after the “/autoinst/” mark (need ctags).

  • NOTE:Need to place the cursor on the module name, multiple-cursor supported to generate multiple instances.

Example:

Before:

test test_instance(/*autoinst*/);

After:

  • Place the cursor on the module name “test”

    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));
    

AutoDef:(shift+f8)


Automatically add instance connections after the /autodef/ mark.

Example:

before:

/*autodef*/



    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

after:

/*autodef*/
wire e;
wire [2:0]d;
wire c;
wire b;
wire [1:0]a;
//assign e=
//assign d=
//assign c=
//assign b=
//assign a=



test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

AddFileHeader:(shift+f9)


Add your personal information in the setting file(the user's setting file is better),like below or leave any of them empty:

{
        "Author":"Mike",
        "Company":"Microsoft",
        "Email":"whatever@yahoo.com"
    }

thus generates the file header like this:

//==================================================================================================
    //  Filename      : test.v
    //  Created On    : 2013-04-01 21:37:31
    //  Last Modified : 
    //  Revision      : 
    //  Author        : Mike
    //  Company       : Microsoft
    //  Email         : whatever@yahoo.com
    //
    //  Description   : 
    //
    //
    //==================================================================================================

Change log

05/08/2013

Add verilog-2001 style port declaration support.
Add comments support, single line commneted-out code will be ignored.